DescriptionThis program addresses the benchmarking of configurable computing systems, systems that can be changed in basic computational structure, either statically or dynamically, without adding physical devices. In its current realizations, a configurable computing system consists of a set of general-purpose processors augmented with a set of field-programmable gate arrays (FPGAs). The program is developing benchmarking technology to evaluate configurable computing systems, leveraging the C3I Parallel Benchmark Suite effort where possible. The objectives are to 1) provide a publicly available set of benchmarks for evaluating configurable computing systems; 2) address the entire range of issues in benchmarking (benchmark specification, procedures, and metrics, along with wide availability); 3) extend benchmarking technology to configurable computing; and 4) implement and evaluate the benchmarks on a configurable computing platform to validate the benchmarking approach and demonstrate the interpretation of the results. Five stressmarks, benchmarks which focus on a specific characteristic or property of the configurable computing system's infrastructure (both tools and architecture), are being developed. These stressmarks attempt to provide additional insight about the infrastructure. The stressmarks being developed focus on the following aspects: versatility, capacity, timing sensitivity, interfacing, and scalability. In addition, a functional benchmark for CAD applications is being developed. These benchmarks are being implemented on an Annapolis Micro Systems WILDFORCE board.
Beyond the six benchmarks mentioned above, four new benchmarks are
under development. These benchmarks are 1) a "micro-kernel" benchmark,
2) an INFOSEC (information security) benchmark, 3) a benchmark
supporting data dependent computations, and 4) a variable precision
arithmetic benchmark. This collection of benchmarks is being implemented
on an Annapolis Micro Systems STARFIRE board.
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PersonnelSanjaya KumarChirag Nanavati Mark Vojta John Golusky Sabera Kazi |
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StatusRelease 1.0 of the benchmark suite (five stressmarks and CAD benchmark) is available. This release contains a benchmarking methodology document, which includes a template of the benchmark specification being used for each benchmark, procedures for performing the benchmarking activity, and metrics to be captured. Benchmark specification documents, one for each of the benchmarks developed, are also provided. These documents contain information regarding specific aspects of the benchmark, such as inputs formats, output formats, acceptance tests for determining whether results are valid, and reporting of results. In addition, "C" code and VHDL code are provided as well. Most of these benchmarks have been implemented on an Annapolis Micro Systems WILDFORCE board. Results have been tabulated and are being reviewed by DARPA.The benchmarks can be accessed through the DARPA/AFRL Benchmarking Program web page, http://www.rl.af.mil/programs/hpcbench. Downloading of the benchmarks requires a password, which can be obtained from Ralph Kohler at AFRL. See the web site for contact information. In addition to Release 1.0, a new release, Release 1.1, is available on CD as of 10/6/99. This release contains the benchmarks provided as part of Release 1.0, updates to the versatility, interfacing, and scalability stressmarks, and draft descriptions of the micro-kernel and INFOSEC benchmarks. Because the VHDL implementations are being tested for these last two benchmarks, only "C" code is provided at this time.
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PresentationsPI Meeting Slides - June 23-25, 1997PI Meeting Slides - November 4-5, 1997 PI Meeting Slides - April 13-14, 1998 PI Meeting Slides - April 6-8, 1999 PI Meeting Slides - October 6-8, 1999 "A Benchmark Suite for Evaluating Configurable Computing Systems - Status, Reflections, and Future Directions," FPGA 2000 - Eighth International Symposium on Field-Programmable Gate Arrays, February 10-11, 2000, Monterey, California. |
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Papers"A Benchmark Suite for Evaluating Configurable Computing Systems - Status, Reflections, and Future Directions," FPGA 2000 - Eighth International Symposium on Field-Programmable Gate Arrays, February 10-11, 2000, Monterey, California.
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Contact Information:
Sanjaya Kumar
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The information contained on this web site does not reflect the position or the policy of the Government and no official endorsement should be inferred. This work is sponsored by DARPA under contract no.
DABT63-96-C-0085. |
