Program Overview
The VIVACE program combines the revolutionary 3-D interconnect capacity (made feasible by the development of VCSELs, smart pixel technology, and high-performance computing technology) into an MPI-based, general-purpose computer architecture for distributed, heterogeneous multiprocessor systems. This work will push 3-D interconnect technology into the mainstream of computing rather than provide only specialized computing subsystems. The 3-D optical interconnect-enabled architecture meets the DoD’s requirements for future data-intensive applications such as advanced UAV-based synthetic aperture radar(SAR) image reconstruction, on-board automatic target recognition (ATR) and cueing, and target tracking in noisy environments. This architecture is also suitable for application to large servers in the commercial arena. In addition, the high-density I/O enabled by the smart pixel integration technology could provide commercial impact in other areas such as processor-to-memory communications. The VIVACE team provides solutions at several levels architecture, box-level packaging, integration of components, system integration, software development, computer-aided design.

Figure 1. Targeted System Architecture

The team also incorporates commercial and military entities on both the user and supplier sides. This encourages broader applicability of the technology development and attention to technology cost and environmental ruggedness. The target architecture, illustrated in Figure 1 for a military application, is based on a switching fabric called MAX-Net in which the processing nodes are distributed across multiple boards within the same chassis, or even other chasses, rather than co-located with the smart pixel switching resources. The network architecture is general and not tailored to a specific application or to a single vendor’s hardware. The processing nodes will consist primarily of COTS-based and general-purpose processors and COTS-based signal processing accelerators, but may include specialized accelerators, such as the FFT engines being developed under the DARPA FSOIA program. The architecture is scalable for increasingly stressing applications, reconfigurable and reusable for changing military missions, and permits transparent upgrades to evolving commercial processors and memory. Its generality and transparency to processor and memory technology is achieved through the use of interface cards that transform a given standard interconnect channel, such as PCI or VME into an optical format suitable for input to the switch. The MAX-Net switch structure will demonstrate a 128 x 128 switch with a bisection bandwidth (BSBW) capacity of ~10 Tbps within a multi-chip module (MCM) area (4" x 4") comparable to that of an 8 x 8 Myrinet switch. Alternatively, a 512-node MAX-Net switch requires approximately 25 cubic inches and 200 W, a three-order-of-magnitude reduction in volume and a factor of 50 in power when compared to a 512-node switch implemented with the required 384 8 x 8 Myrinet switches. This minimum number of required Myrinet switches sacrifices the ability to have self-routing packet switching, while MAX-Net retains self-routing control.

The MAX-Net architecture uses redundant multi-stage routing to achieve arbitrarily low blocking rates. Figure 2 shows the impact of this improved switch performance by the projected SAR I/O and throughput requirements with the BSBW achievable within a 0.5-cubic-foot volume, using the free-space switch. The long-range requirements in Figure 2 are generated by accounting for trends toward increasing sensor resolution and framer ates. The system-level packaging approach ensures scalability and adaptability of the approach to future technology developments, while facilitating integration with current off-the-shelf components. Fiber optic interconnects between the interface cards and the switch enable more processing capacity to be incorporated onto the otherwise pin-limited boards and delivers the high density of high-speed lines required to feed the switch, a point also illustrated in the interconnect capacity graph in Figure 2. We will draw on parallel fiber ribbon, connector, and I/O buffer technology being developed under the Honeywell OMNET program. The optimal combination of micro- and macro-optical design prevents the switch density from being diffraction limited.

Figure 2. Bandwidth requirement and interconnect means.

The VIVACE program will enhance the yield, produciblity, and reliability of the optical device and smart pixel integration technology currently being developed under the DARPA FSOIA program. Similar to the transition from discrete transistors into CMOS VLSI circuits, we will pursue lasers and receivers that consume no DC power in the off-state and are smaller and more densely packed. For increased yield, we will follow the lead of the integrated circuit industry to pursue techniques such as planar semiconductor fabrication processes and the use of projection lithography. The expected output will be an order of magnitude increase in the smart pixel integration level (i.e., number of pixels/chip).

A comprehensive thermo-mechanical model of the integrated optoelectronic device will be developed and validated to provide additional design capability to the community.

The VIVACE project will demonstrate the processing and communication throughput performance of the developed system for future DoD applications, such as automatic target recognition and cueing; sophisticated, computationally intensive methods for target detection, recognition, and tracking; and high-resolution synthetic aperture radar imaging. Emphasis in a system demonstration will be given to a SAR application. In addition to the planned military demonstration, relevant commercial application requirements will be provided by Sun Microsystems and Intel, commercial users of advanced interconnect technology.

Program Approach
The final demonstration of a SAR military application will be carried out on a small-scale testbed, consisting of eight computer nodes and a switch module. The computer nodes will be COTS based and will contain COTS cards for general-purpose processing, signal processing acceleration, and memory. Each node will also contain an optical interface card. The current leading candidates for the COTS cards are a two-chip symmetric Pentium Pro (or its successor) card, multiple 16-chip Tigersharc (or its successor) accelerator cards, and multiple bulk memory cards.

Figure 3 illustrates the theme of the VIVACE program. The nodes are highly flexible, allowing the transparent addition of processing and memory, heterogeneous processors, and user/custom I/O. Although the testbed will contain only eight nodes, the system can be scaled up to 256 nodes under the current prototype optical switching design.

Each of the eight computer nodes in the testbed will be interconnected with the switch module via its optical node interface card (NIC). The heart of the optical switch is an optoelectronic MCM that consists of 4 x 4 arrays of large-scale smart pixel arrays in the center and 16 interface chips at its periphery. The interconnects between the computer nodes and the switch module are based on the parallel optical fiber link that interfaces the I/O chip on the optical NIC and the interface chip in the switch MCM. This configuration draws heavily on technology developed by the DARPA OMNET program. The 16 smart pixel array chips will be the result of heterogeneous integration of three key components monolithically integrated large-scale 2D VCSEL Photodetector (PD) array, CMOS VLSI switch ASIC, and large scale micro-lens array.

Our objective is to maximize the capacity and throughput of the 3D optical switch module. This switch takes advantage of enormous bandwidth within the intra-module free-space optics domain, and utilizes high-density parallel optical links to implement the switch I/O ports. The capacity of the switch prototype is up to approximately 128 ports. The bi-directional throughput of each port is from 2.56 Gbps up to 10.24 Gbps, which will be physically mapped onto one to six optical channels (with a direct trade-off between the number of ports and throughput per port). The node throughput will conform to future data bus standard(s), such as PCI and/or VME bus. We will optimize the optical channel bit rate by taking advantage of the maximum bit rate offered by state-of-the-art Si CMOS VLSI technology, and the minimized total power dissipation of the VLSI photonic switch. The intra-switch free-space interconnects are based on 16 smart pixel arrays and related routing optics. The 128-port switch requires 16 2D smart-pixel chips (32 x 32 each) for a total switch matrix size of 128 x 128.

Figure 3. Summary view of VIVACE program approach.